Verilog - 8case_4true / boolean expression / schematic

 

 

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Verilog Basic - hw(1)

 

 

과제(1)

- 3bit binary(A,B,C)로 표현된 7가지 경우에 대하여 m0,m2,m6,m7에 대해서만 true(y=1)

 

 

Boolean Expression

 

Y = A'C' + AB

 

 

 

wire 구현

 

: wire는 초반에 선언을 모두 하지 않고, main body에서 gate들을 구현하며 필요로 하는 것을 추가하여 선언한다.

 

 

 

 

Verilog Design source

 

module _8case_4true(out, i0, i1, i2);

    //output,input declaration
    output out;
    input i0,i1,i2;

    //wire declaration
    wire n0,n2;
    wire a0,a1;
    
    //gate declaration
    //not gate
    not (n0,i0);
    not (n2, i2);
    
    //and gate
    and (a0, n0, n2);
    and (a1, i0, i1);

    //or gate
    or (out, a0, a1);
    
endmodule

 

 

 

schematic

 

 

 

 

 

 

synthesis report

 

???

 

 

 

test bench code

 

module tb_8case_4true();

//Stimulus Declaration (input)
reg IN0, IN1, IN2;

//Response Declaration (output)
wire OUTPUT;

//object
_8case_4true mycase (OUTPUT, IN0, IN1, IN2);

//stimulus
initial begin
    IN0 = 0; IN1 = 0; IN2 = 0;
    #5 IN0 = 0; IN1 = 0; IN2 = 1;
    #5 IN0 = 0; IN1 = 1; IN2 = 0;
    #5 IN0 = 0; IN1 = 1; IN2 = 1;
    #5 IN0 = 1; IN1 = 0; IN2 = 0;
    #5 IN0 = 1; IN1 = 0; IN2 = 1;
    #5 IN0 = 1; IN1 = 1; IN2 = 0;
    #5 IN0 = 1; IN1 = 1; IN2 = 1;
end

endmodule

 

 

simulation result