Verilog - mux4_to_1 & test bench

 

 

---

4:1 MUX

 

 

 

4:1MUX Design Source

 

module mux_4to1 (out, i0, i1, i2, i3, s1, s0);
    
    //output,input declaration
    output out;
    input i0, i1, i2, i3;
    input s1, s0;
    
    //wire(net) declaration
    wire n1, n0;   //not gate out wire
    wire a0, a1, a2, a3;   //and gate out wire
    
    //not gate
    not (n1, s1);   
    not (n0, s0);
    
    //and gate
    and (a0, i0, n1, n0);  //00
    and (a1, i1, n1, s0);   //01
    and (a2, i2, s1, n0);   //10
    and (a3, i3, s1, s0);    //11
    
    //or gate
    or (out, a0, a1, a2, a3);
    
endmodule

 

 

 

 

 

Schematic

 

 

 

 

 

Synthesis report

???

 

 

 

Test bench Code

 

module tb_mux_4to1();

//Stimulus Declaration (input)
 reg IN0, IN1, IN2, IN3;
 reg S1, S0; 

//Response Declaration (output)
 wire OUTPUT; 

mux_4to1 mymux (OUTPUT, IN0, IN1, IN2, IN3, S1, S0);

//stimulus
initial begin
     IN0 = 1;
     IN1 = 0;
     IN2 = 1;
     IN3 = 0;

     S1 = 0; S0 = 0;
     #5 S1 = 0; S0 = 1;
     #5 S1 = 1; S0 = 0;
     #5 S1 = 1; S0 = 1;
end
   
endmodule

 

 

 

 

 

Simulation Result

 

 

 

 

Discussion

 

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